NAND Chips: Let's Pile Them Up

Over the last 2 years, storage capacity of NAND flash memories have dramatically improved, one can simply look at the storage space available on USB keys which now can be found up to 8 to 16GB! Improvements on engraving processes allowed delivering such high capacity chips. NAND chips manufacturers can still improve such processes moving to 45nm, or even 32nm. However, such planar NAND technology will have a higher cost, and resulting price/GB might not be commercially viable.
So, manufacturers decided to pile layers of planar NAND chips to create stacks of NAND. If Samsung, IBM and Hynix have already announced such stacks of NAND flash, interconnection of each layer together is the main issue.
During the last VLSI symposium, Toshiba presented a new 3D memory chips array technology allowing to improve both cell density and data capacity with almost no modification on the die size. The main advantage of Toshiba's technology is to increase the density without increasing chip dimension, as the number of interconnected elements increases proportionally to stack height. Based on this technology one could expect to dramatically increase memory density and so storage capacity. Toshiba claims that a 32-layers stack could have a cell density multiplied by 10 without modifying the chip size.
CPU manufacturers are also investigating such 3D stacking of cores to further increase the core number without modifying the die size; but of course this is a much more challenging project.