PCI Express 2.0 Specifications Validated

The PCI Sig group unveiled specifications of the PCI Express 2.0 format.
These new architecture improvements include:
- Dynamic link speed management allows developers to control the speed at which the link is operating
- Link bandwidth notification alerts platform software (operating system, device drivers, etc) of changes in link speed and width
- Capability structure expansion increases control registers to better manage devices, slots and the interconnect
- Access control services allows for optional controls to manage peer-to-peer transactions
- Completion timeout control allows developers to define a required disable mechanism for transaction timeouts
- Function-level reset provides an optional mechanism to reset functions within a multi-function device
- Power limit redefinition enables slot power limit values to accommodate devices that consume higher power
- The PCIe Base 2.0 specification is available for download at http://www.pcisig.com/specifications/pciexpress/base2/ (only for registered companies).
With this new format, bandwidth of each PCI-Express line is doubled (from 256 to 512MB/s); however even with the latest graphic card models it was far to be saturated.
Last but not least, the PCI-Express will be able to provide more power, making it possible to avoid using additional power line for the eager graphic cards found in our computers; but with nVidia and ATI it might only be temporary...
Of course PCI-Express 2.0 will be back compatible, and Intel should offer first dedicated chipsets in 2007, so we should quickly see them in our Macs.