Understand SSD
- page 01: Flash memory
- page 02: MLC and SLC
- page 03: Sectors, pages, blocks...
- page 04: Wear-leveling
- page 05: TRIM
- page 06: Garbage collector
- page 07: Every day usage
- page 08: Conclusion
Wear-leveling
In addition to the different addressing systems, SSDs have an additional specificity when compared to disc-based HDDs: cells are aging with every erasing procedure, reducing the lifetime and capacity of the cell to store the data saved on it. Each cell is then designed to offer a maximal erasing cycles. According to the JEDEC specifications, this number must be defined in order to ensure secured storage of data for 10 years for a cell which would have already undergo 10% of its erasing cycles; and at least 1 year for a cell which already reached its maximal number of erasing cycles. For MLC chips, the maximal number of tolerated erasing cycles is at least 10,000, while it reaches 100,000 for SLC chips. While this 10-fold difference might look huge, it will have almost no impact on consumer electronics-dedicated units as one will likely have moved to another unit offering higher performance or storage before the end of this 10 year period, even for MLC-based models.
The problem: our current OS are not designed to work flawlessly with SSD, and it is often required to rewrite the same logical sectors, while others are almost never used. The SSD memory controller implements algorithms known as "wear-leveling" to spread writing steps on the entire "area" of the SSD, to avoid premature end of life of some cells.
Unlike for disc-based SSDs, a defined logical sector will not necessarily be programed/saved on the same cells, and might move depending on writing cycles.
The side effect of this system is a decrease in performance. Indeed, the controller will be checking which pages are the best suited to be used to store the assigned data for each request. This is particularly the case for MLC-based models for multiple random operations. In order to avoid a stiff decrease in performance, it is necessary to choose a SSD for which a substantial cache memory will have been associated to the controller, giving it the ability to store information about available pages and their potential free space. If the controller does not have cache memory, such as SSDs based on the Jmicron JMF602 controller, performance will massively drop in case of simultaneous multiple random operations (often required by the OS), and become even less competitive than equivalent disc-based HDDs, with access times reaching hundreds of milliseconds.
There is another side effect due to the wear-leveling system: it fragments data over the storage volume, leading to an increase in access time and an associated drop in writing performance. Indeed, let's take a 1 MB file to be saved on a SSD offering 2 KB pages and blocks of 512 KB. On a brand new SSD, all cells are blanked, so the file will be stored sequentially on adjacent cells. Then overtime, especially is the file is modified then saved again, the controller will favor blank pages, then later on pages that can be erased. So, the more the SSD has been used, the more difficult it will be to find 2 or more sequentially blanked pages to be used. So, the file will most likely be fragmented. Over time, it becomes almost impossible to find a block that can entirely be used, so every writing steps will required blocks to be erased and rewritten on other locations... it is time consuming and impacts performances.
When rewriting a sector on a different physical location than the previous writing process , the SSD controller tags the page containing the sector to be rewritten as erasable. In addition, with the wear-leveling, the controller must prevent accelerated aging of the data/cells. As we explained it above, data have a limited lifetime after being written. So, during low request periods, the controller will check the age of saved data on the volume, then rewrite those getting close to the max lifetime (with a substantial margin to ensure integrity of the data and to follow JEDEC regulations).
